803 lines
37 KiB
C
803 lines
37 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_hal_dma.h
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* @author MCD Application Team
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* @brief Header file of DMA HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file in
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* the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_HAL_DMA_H
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#define __STM32F4xx_HAL_DMA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal_def.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup DMA
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup DMA_Exported_Types DMA Exported Types
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* @brief DMA Exported Types
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* @{
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*/
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/**
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* @brief DMA Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t Channel; /*!< Specifies the channel used for the specified stream.
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This parameter can be a value of @ref DMA_Channel_selection */
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uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
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from memory to memory or from peripheral to memory.
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This parameter can be a value of @ref DMA_Data_transfer_direction */
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uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
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uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
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This parameter can be a value of @ref DMA_Memory_incremented_mode */
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uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
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This parameter can be a value of @ref DMA_Peripheral_data_size */
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uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
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This parameter can be a value of @ref DMA_Memory_data_size */
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uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
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This parameter can be a value of @ref DMA_mode
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@note The circular buffer mode cannot be used if the memory-to-memory
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data transfer is configured on the selected Stream */
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uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
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This parameter can be a value of @ref DMA_Priority_level */
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uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
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This parameter can be a value of @ref DMA_FIFO_direct_mode
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@note The Direct mode (FIFO mode disabled) cannot be used if the
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memory-to-memory data transfer is configured on the selected stream */
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uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
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This parameter can be a value of @ref DMA_FIFO_threshold_level */
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uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
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It specifies the amount of data to be transferred in a single non interruptible
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transaction.
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This parameter can be a value of @ref DMA_Memory_burst
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@note The burst mode is possible only if the address Increment mode is enabled. */
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uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
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It specifies the amount of data to be transferred in a single non interruptible
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transaction.
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This parameter can be a value of @ref DMA_Peripheral_burst
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@note The burst mode is possible only if the address Increment mode is enabled. */
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}DMA_InitTypeDef;
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/**
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* @brief HAL DMA State structures definition
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*/
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typedef enum
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{
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HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
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HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
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HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
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HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
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HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
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HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
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}HAL_DMA_StateTypeDef;
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/**
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* @brief HAL DMA Error Code structure definition
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*/
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typedef enum
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{
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HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
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HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
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}HAL_DMA_LevelCompleteTypeDef;
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/**
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* @brief HAL DMA Error Code structure definition
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*/
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typedef enum
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{
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HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
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HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
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HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
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HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
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HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
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HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
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HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
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}HAL_DMA_CallbackIDTypeDef;
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/**
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* @brief DMA handle Structure definition
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*/
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typedef struct __DMA_HandleTypeDef
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{
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DMA_Stream_TypeDef *Instance; /*!< Register base address */
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DMA_InitTypeDef Init; /*!< DMA communication parameters */
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HAL_LockTypeDef Lock; /*!< DMA locking object */
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__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
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void *Parent; /*!< Parent object state */
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void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
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void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
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void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
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void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
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void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
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void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
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__IO uint32_t ErrorCode; /*!< DMA Error code */
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uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
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uint32_t StreamIndex; /*!< DMA Stream Index */
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}DMA_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup DMA_Exported_Constants DMA Exported Constants
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* @brief DMA Exported constants
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* @{
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*/
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/** @defgroup DMA_Error_Code DMA Error Code
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* @brief DMA Error Code
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* @{
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*/
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#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
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#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
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#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
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#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
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#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
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#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
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#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
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#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
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/**
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* @}
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*/
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/** @defgroup DMA_Channel_selection DMA Channel selection
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* @brief DMA channel selection
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* @{
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*/
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#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
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#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
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#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
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#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
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#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
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#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
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#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
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#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
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#if defined (DMA_SxCR_CHSEL_3)
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#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
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#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
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#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */
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#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */
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#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */
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#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */
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#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */
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#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */
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#endif /* DMA_SxCR_CHSEL_3 */
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/**
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* @}
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*/
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/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
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* @brief DMA data transfer direction
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* @{
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*/
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#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
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#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
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#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
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/**
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* @}
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*/
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/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
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* @brief DMA peripheral incremented mode
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* @{
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*/
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#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
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#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
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/**
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* @}
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*/
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/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
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* @brief DMA memory incremented mode
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* @{
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*/
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#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
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#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
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/**
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* @}
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*/
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/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
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* @brief DMA peripheral data size
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* @{
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*/
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#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
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#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
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#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
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/**
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* @}
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*/
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/** @defgroup DMA_Memory_data_size DMA Memory data size
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* @brief DMA memory data size
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* @{
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*/
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#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
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#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
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#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
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/**
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* @}
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*/
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/** @defgroup DMA_mode DMA mode
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* @brief DMA mode
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* @{
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*/
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#define DMA_NORMAL 0x00000000U /*!< Normal mode */
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#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
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#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
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/**
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* @}
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*/
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/** @defgroup DMA_Priority_level DMA Priority level
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* @brief DMA priority levels
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* @{
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*/
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#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
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#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
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#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
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#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
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/**
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* @}
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*/
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/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
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* @brief DMA FIFO direct mode
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* @{
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*/
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#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
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#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
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/**
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* @}
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*/
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/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
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* @brief DMA FIFO level
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* @{
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*/
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#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
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#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
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#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
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#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
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/**
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* @}
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*/
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/** @defgroup DMA_Memory_burst DMA Memory burst
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* @brief DMA memory burst
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* @{
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*/
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#define DMA_MBURST_SINGLE 0x00000000U
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#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
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#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
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#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
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/**
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* @}
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*/
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/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
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* @brief DMA peripheral burst
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* @{
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*/
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#define DMA_PBURST_SINGLE 0x00000000U
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#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
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#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
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#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
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/**
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* @}
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*/
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/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
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* @brief DMA interrupts definition
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* @{
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*/
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#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
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#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
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#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
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#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
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#define DMA_IT_FE 0x00000080U
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/**
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* @}
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*/
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/** @defgroup DMA_flag_definitions DMA flag definitions
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* @brief DMA flag definitions
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* @{
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*/
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#define DMA_FLAG_FEIF0_4 0x00000001U
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#define DMA_FLAG_DMEIF0_4 0x00000004U
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#define DMA_FLAG_TEIF0_4 0x00000008U
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#define DMA_FLAG_HTIF0_4 0x00000010U
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#define DMA_FLAG_TCIF0_4 0x00000020U
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#define DMA_FLAG_FEIF1_5 0x00000040U
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#define DMA_FLAG_DMEIF1_5 0x00000100U
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#define DMA_FLAG_TEIF1_5 0x00000200U
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#define DMA_FLAG_HTIF1_5 0x00000400U
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#define DMA_FLAG_TCIF1_5 0x00000800U
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#define DMA_FLAG_FEIF2_6 0x00010000U
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#define DMA_FLAG_DMEIF2_6 0x00040000U
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#define DMA_FLAG_TEIF2_6 0x00080000U
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#define DMA_FLAG_HTIF2_6 0x00100000U
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#define DMA_FLAG_TCIF2_6 0x00200000U
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#define DMA_FLAG_FEIF3_7 0x00400000U
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#define DMA_FLAG_DMEIF3_7 0x01000000U
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#define DMA_FLAG_TEIF3_7 0x02000000U
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#define DMA_FLAG_HTIF3_7 0x04000000U
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#define DMA_FLAG_TCIF3_7 0x08000000U
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @brief Reset DMA handle state
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* @param __HANDLE__ specifies the DMA handle.
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* @retval None
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*/
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#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
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/**
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* @brief Return the current DMA Stream FIFO filled level.
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* @param __HANDLE__ DMA handle
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* @retval The FIFO filling state.
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* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
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* and not empty.
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* - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
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* - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
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* - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
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* - DMA_FIFOStatus_Empty: when FIFO is empty
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* - DMA_FIFOStatus_Full: when FIFO is full
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*/
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#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
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/**
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* @brief Enable the specified DMA Stream.
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* @param __HANDLE__ DMA handle
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* @retval None
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*/
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#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
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/**
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* @brief Disable the specified DMA Stream.
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* @param __HANDLE__ DMA handle
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* @retval None
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*/
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#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
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/* Interrupt & Flag management */
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/**
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* @brief Return the current DMA Stream transfer complete flag.
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* @param __HANDLE__ DMA handle
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* @retval The specified transfer complete flag index.
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*/
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#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
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(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
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DMA_FLAG_TCIF3_7)
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/**
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* @brief Return the current DMA Stream half transfer complete flag.
|
|
* @param __HANDLE__ DMA handle
|
|
* @retval The specified half transfer complete flag index.
|
|
*/
|
|
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
|
|
DMA_FLAG_HTIF3_7)
|
|
|
|
/**
|
|
* @brief Return the current DMA Stream transfer error flag.
|
|
* @param __HANDLE__ DMA handle
|
|
* @retval The specified transfer error flag index.
|
|
*/
|
|
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
|
|
DMA_FLAG_TEIF3_7)
|
|
|
|
/**
|
|
* @brief Return the current DMA Stream FIFO error flag.
|
|
* @param __HANDLE__ DMA handle
|
|
* @retval The specified FIFO error flag index.
|
|
*/
|
|
#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
|
|
DMA_FLAG_FEIF3_7)
|
|
|
|
/**
|
|
* @brief Return the current DMA Stream direct mode error flag.
|
|
* @param __HANDLE__ DMA handle
|
|
* @retval The specified direct mode error flag index.
|
|
*/
|
|
#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
|
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
|
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
|
|
DMA_FLAG_DMEIF3_7)
|
|
|
|
/**
|
|
* @brief Get the DMA Stream pending flags.
|
|
* @param __HANDLE__ DMA handle
|
|
* @param __FLAG__ Get the specified flag.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
|
|
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
|
|
* @arg DMA_FLAG_TEIFx: Transfer error flag.
|
|
* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
|
|
* @arg DMA_FLAG_FEIFx: FIFO error flag.
|
|
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
|
|
* @retval The state of FLAG (SET or RESET).
|
|
*/
|
|
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
|
|
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
|
|
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
|
|
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
|
|
|
|
/**
|
|
* @brief Clear the DMA Stream pending flags.
|
|
* @param __HANDLE__ DMA handle
|
|
* @param __FLAG__ specifies the flag to clear.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
|
|
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
|
|
* @arg DMA_FLAG_TEIFx: Transfer error flag.
|
|
* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
|
|
* @arg DMA_FLAG_FEIFx: FIFO error flag.
|
|
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
|
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
|
|
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
|
|
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
|
|
|
|
/**
|
|
* @brief Enable the specified DMA Stream interrupts.
|
|
* @param __HANDLE__ DMA handle
|
|
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
|
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
|
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
|
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
|
* @arg DMA_IT_DME: Direct mode error interrupt.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
|
((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
|
|
|
|
/**
|
|
* @brief Disable the specified DMA Stream interrupts.
|
|
* @param __HANDLE__ DMA handle
|
|
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
|
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
|
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
|
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
|
* @arg DMA_IT_DME: Direct mode error interrupt.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
|
((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
|
|
|
|
/**
|
|
* @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
|
|
* @param __HANDLE__ DMA handle
|
|
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
|
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
|
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
|
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
|
* @arg DMA_IT_DME: Direct mode error interrupt.
|
|
* @retval The state of DMA_IT.
|
|
*/
|
|
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
|
((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
|
|
((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
|
|
|
|
/**
|
|
* @brief Writes the number of data units to be transferred on the DMA Stream.
|
|
* @param __HANDLE__ DMA handle
|
|
* @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
|
|
* Number of data items depends only on the Peripheral data format.
|
|
*
|
|
* @note If Peripheral data format is Bytes: number of data units is equal
|
|
* to total number of bytes to be transferred.
|
|
*
|
|
* @note If Peripheral data format is Half-Word: number of data units is
|
|
* equal to total number of bytes to be transferred / 2.
|
|
*
|
|
* @note If Peripheral data format is Word: number of data units is equal
|
|
* to total number of bytes to be transferred / 4.
|
|
*
|
|
* @retval The number of remaining data units in the current DMAy Streamx transfer.
|
|
*/
|
|
#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
|
|
|
|
/**
|
|
* @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
|
|
* @param __HANDLE__ DMA handle
|
|
*
|
|
* @retval The number of remaining data units in the current DMA Stream transfer.
|
|
*/
|
|
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
|
|
|
|
|
|
/* Include DMA HAL Extension module */
|
|
#include "stm32f4xx_hal_dma_ex.h"
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
|
|
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
|
* @brief DMA Exported functions
|
|
* @{
|
|
*/
|
|
|
|
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
* @brief Initialization and de-initialization functions
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
|
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
|
|
* @brief I/O operation functions
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
|
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
|
HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
|
|
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
|
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
|
|
* @brief Peripheral State functions
|
|
* @{
|
|
*/
|
|
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
|
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
|
/**
|
|
* @}
|
|
*/
|
|
/**
|
|
* @}
|
|
*/
|
|
/* Private Constants -------------------------------------------------------------*/
|
|
/** @defgroup DMA_Private_Constants DMA Private Constants
|
|
* @brief DMA private defines and constants
|
|
* @{
|
|
*/
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private macros ------------------------------------------------------------*/
|
|
/** @defgroup DMA_Private_Macros DMA Private Macros
|
|
* @brief DMA private macros
|
|
* @{
|
|
*/
|
|
#if defined (DMA_SxCR_CHSEL_3)
|
|
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
|
|
((CHANNEL) == DMA_CHANNEL_1) || \
|
|
((CHANNEL) == DMA_CHANNEL_2) || \
|
|
((CHANNEL) == DMA_CHANNEL_3) || \
|
|
((CHANNEL) == DMA_CHANNEL_4) || \
|
|
((CHANNEL) == DMA_CHANNEL_5) || \
|
|
((CHANNEL) == DMA_CHANNEL_6) || \
|
|
((CHANNEL) == DMA_CHANNEL_7) || \
|
|
((CHANNEL) == DMA_CHANNEL_8) || \
|
|
((CHANNEL) == DMA_CHANNEL_9) || \
|
|
((CHANNEL) == DMA_CHANNEL_10)|| \
|
|
((CHANNEL) == DMA_CHANNEL_11)|| \
|
|
((CHANNEL) == DMA_CHANNEL_12)|| \
|
|
((CHANNEL) == DMA_CHANNEL_13)|| \
|
|
((CHANNEL) == DMA_CHANNEL_14)|| \
|
|
((CHANNEL) == DMA_CHANNEL_15))
|
|
#else
|
|
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
|
|
((CHANNEL) == DMA_CHANNEL_1) || \
|
|
((CHANNEL) == DMA_CHANNEL_2) || \
|
|
((CHANNEL) == DMA_CHANNEL_3) || \
|
|
((CHANNEL) == DMA_CHANNEL_4) || \
|
|
((CHANNEL) == DMA_CHANNEL_5) || \
|
|
((CHANNEL) == DMA_CHANNEL_6) || \
|
|
((CHANNEL) == DMA_CHANNEL_7))
|
|
#endif /* DMA_SxCR_CHSEL_3 */
|
|
|
|
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
|
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
|
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
|
|
|
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
|
|
|
|
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
|
((STATE) == DMA_PINC_DISABLE))
|
|
|
|
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
|
((STATE) == DMA_MINC_DISABLE))
|
|
|
|
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
|
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
|
((SIZE) == DMA_PDATAALIGN_WORD))
|
|
|
|
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
|
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
|
((SIZE) == DMA_MDATAALIGN_WORD ))
|
|
|
|
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
|
((MODE) == DMA_CIRCULAR) || \
|
|
((MODE) == DMA_PFCTRL))
|
|
|
|
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
|
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
|
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
|
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
|
|
|
#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
|
|
((STATE) == DMA_FIFOMODE_ENABLE))
|
|
|
|
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
|
|
((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
|
|
((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
|
|
((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
|
|
|
|
#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
|
|
((BURST) == DMA_MBURST_INC4) || \
|
|
((BURST) == DMA_MBURST_INC8) || \
|
|
((BURST) == DMA_MBURST_INC16))
|
|
|
|
#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
|
|
((BURST) == DMA_PBURST_INC4) || \
|
|
((BURST) == DMA_PBURST_INC8) || \
|
|
((BURST) == DMA_PBURST_INC16))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
/** @defgroup DMA_Private_Functions DMA Private Functions
|
|
* @brief DMA private functions
|
|
* @{
|
|
*/
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32F4xx_HAL_DMA_H */
|
|
|