424 lines
18 KiB
C
424 lines
18 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_ll_dma.c
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* @author MCD Application Team
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* @brief DMA LL module driver.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file in
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* the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_ll_dma.h"
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#include "stm32f4xx_ll_bus.h"
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#ifdef USE_FULL_ASSERT
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#include "stm32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif
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/** @addtogroup STM32F4xx_LL_Driver
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* @{
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*/
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#if defined (DMA1) || defined (DMA2)
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/** @defgroup DMA_LL DMA
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup DMA_LL_Private_Macros
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* @{
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*/
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#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
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((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
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((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
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#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
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((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
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((__VALUE__) == LL_DMA_MODE_PFCTRL))
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#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
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((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
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#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
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((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
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#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
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((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
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((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
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#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
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((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
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((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
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#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
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#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
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((__VALUE__) == LL_DMA_CHANNEL_1) || \
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((__VALUE__) == LL_DMA_CHANNEL_2) || \
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((__VALUE__) == LL_DMA_CHANNEL_3) || \
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((__VALUE__) == LL_DMA_CHANNEL_4) || \
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((__VALUE__) == LL_DMA_CHANNEL_5) || \
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((__VALUE__) == LL_DMA_CHANNEL_6) || \
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((__VALUE__) == LL_DMA_CHANNEL_7))
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#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
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((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
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((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
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((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
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#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
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(((STREAM) == LL_DMA_STREAM_0) || \
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((STREAM) == LL_DMA_STREAM_1) || \
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((STREAM) == LL_DMA_STREAM_2) || \
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((STREAM) == LL_DMA_STREAM_3) || \
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((STREAM) == LL_DMA_STREAM_4) || \
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((STREAM) == LL_DMA_STREAM_5) || \
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((STREAM) == LL_DMA_STREAM_6) || \
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((STREAM) == LL_DMA_STREAM_7) || \
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((STREAM) == LL_DMA_STREAM_ALL))) ||\
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(((INSTANCE) == DMA2) && \
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(((STREAM) == LL_DMA_STREAM_0) || \
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((STREAM) == LL_DMA_STREAM_1) || \
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((STREAM) == LL_DMA_STREAM_2) || \
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((STREAM) == LL_DMA_STREAM_3) || \
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((STREAM) == LL_DMA_STREAM_4) || \
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((STREAM) == LL_DMA_STREAM_5) || \
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((STREAM) == LL_DMA_STREAM_6) || \
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((STREAM) == LL_DMA_STREAM_7) || \
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((STREAM) == LL_DMA_STREAM_ALL))))
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#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
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((STATE) == LL_DMA_FIFOMODE_ENABLE))
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#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
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((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
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((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
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((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
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#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
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((BURST) == LL_DMA_MBURST_INC4) || \
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((BURST) == LL_DMA_MBURST_INC8) || \
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((BURST) == LL_DMA_MBURST_INC16))
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#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
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((BURST) == LL_DMA_PBURST_INC4) || \
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((BURST) == LL_DMA_PBURST_INC8) || \
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((BURST) == LL_DMA_PBURST_INC16))
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup DMA_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup DMA_LL_EF_Init
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* @{
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*/
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/**
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* @brief De-initialize the DMA registers to their default reset values.
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* @param DMAx DMAx Instance
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* @param Stream This parameter can be one of the following values:
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* @arg @ref LL_DMA_STREAM_0
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* @arg @ref LL_DMA_STREAM_1
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* @arg @ref LL_DMA_STREAM_2
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* @arg @ref LL_DMA_STREAM_3
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* @arg @ref LL_DMA_STREAM_4
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* @arg @ref LL_DMA_STREAM_5
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* @arg @ref LL_DMA_STREAM_6
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* @arg @ref LL_DMA_STREAM_7
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* @arg @ref LL_DMA_STREAM_ALL
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: DMA registers are de-initialized
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* - ERROR: DMA registers are not de-initialized
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*/
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uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
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{
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DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
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ErrorStatus status = SUCCESS;
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/* Check the DMA Instance DMAx and Stream parameters*/
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assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
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if (Stream == LL_DMA_STREAM_ALL)
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{
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if (DMAx == DMA1)
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{
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/* Force reset of DMA clock */
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LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
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/* Release reset of DMA clock */
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LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
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}
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else if (DMAx == DMA2)
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{
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/* Force reset of DMA clock */
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LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
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/* Release reset of DMA clock */
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LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
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}
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else
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{
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status = ERROR;
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}
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}
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else
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{
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/* Disable the selected Stream */
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LL_DMA_DisableStream(DMAx,Stream);
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/* Get the DMA Stream Instance */
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tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
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/* Reset DMAx_Streamy configuration register */
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LL_DMA_WriteReg(tmp, CR, 0U);
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/* Reset DMAx_Streamy remaining bytes register */
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LL_DMA_WriteReg(tmp, NDTR, 0U);
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/* Reset DMAx_Streamy peripheral address register */
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LL_DMA_WriteReg(tmp, PAR, 0U);
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/* Reset DMAx_Streamy memory address register */
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LL_DMA_WriteReg(tmp, M0AR, 0U);
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/* Reset DMAx_Streamy memory address register */
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LL_DMA_WriteReg(tmp, M1AR, 0U);
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/* Reset DMAx_Streamy FIFO control register */
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LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
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/* Reset Channel register field for DMAx Stream*/
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LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
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if(Stream == LL_DMA_STREAM_0)
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{
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/* Reset the Stream0 pending flags */
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DMAx->LIFCR = 0x0000003FU;
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}
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else if(Stream == LL_DMA_STREAM_1)
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{
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/* Reset the Stream1 pending flags */
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DMAx->LIFCR = 0x00000F40U;
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}
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else if(Stream == LL_DMA_STREAM_2)
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{
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/* Reset the Stream2 pending flags */
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DMAx->LIFCR = 0x003F0000U;
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}
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else if(Stream == LL_DMA_STREAM_3)
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{
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/* Reset the Stream3 pending flags */
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DMAx->LIFCR = 0x0F400000U;
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}
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else if(Stream == LL_DMA_STREAM_4)
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{
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/* Reset the Stream4 pending flags */
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DMAx->HIFCR = 0x0000003FU;
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}
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else if(Stream == LL_DMA_STREAM_5)
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{
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/* Reset the Stream5 pending flags */
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DMAx->HIFCR = 0x00000F40U;
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}
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else if(Stream == LL_DMA_STREAM_6)
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{
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/* Reset the Stream6 pending flags */
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DMAx->HIFCR = 0x003F0000U;
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}
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else if(Stream == LL_DMA_STREAM_7)
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{
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/* Reset the Stream7 pending flags */
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DMAx->HIFCR = 0x0F400000U;
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}
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else
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{
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status = ERROR;
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}
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}
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return status;
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}
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/**
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* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
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* @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
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* @arg @ref __LL_DMA_GET_INSTANCE
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* @arg @ref __LL_DMA_GET_STREAM
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* @param DMAx DMAx Instance
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* @param Stream This parameter can be one of the following values:
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* @arg @ref LL_DMA_STREAM_0
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* @arg @ref LL_DMA_STREAM_1
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* @arg @ref LL_DMA_STREAM_2
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* @arg @ref LL_DMA_STREAM_3
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* @arg @ref LL_DMA_STREAM_4
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* @arg @ref LL_DMA_STREAM_5
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* @arg @ref LL_DMA_STREAM_6
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* @arg @ref LL_DMA_STREAM_7
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* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: DMA registers are initialized
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* - ERROR: Not applicable
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*/
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uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
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{
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/* Check the DMA Instance DMAx and Stream parameters*/
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assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
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/* Check the DMA parameters from DMA_InitStruct */
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assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
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assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
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assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
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assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
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assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
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assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
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assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
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assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
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assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
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assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
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/* Check the memory burst, peripheral burst and FIFO threshold parameters only
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when FIFO mode is enabled */
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if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
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{
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assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
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assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
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assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
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}
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/*---------------------------- DMAx SxCR Configuration ------------------------
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* Configure DMAx_Streamy: data transfer direction, data transfer mode,
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* peripheral and memory increment mode,
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* data size alignment and priority level with parameters :
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* - Direction: DMA_SxCR_DIR[1:0] bits
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* - Mode: DMA_SxCR_CIRC bit
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* - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
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* - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
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* - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
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* - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
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* - Priority: DMA_SxCR_PL[1:0] bits
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*/
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LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
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DMA_InitStruct->Mode | \
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DMA_InitStruct->PeriphOrM2MSrcIncMode | \
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DMA_InitStruct->MemoryOrM2MDstIncMode | \
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DMA_InitStruct->PeriphOrM2MSrcDataSize | \
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DMA_InitStruct->MemoryOrM2MDstDataSize | \
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DMA_InitStruct->Priority
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);
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if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
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{
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/*---------------------------- DMAx SxFCR Configuration ------------------------
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* Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
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* - FIFOMode: DMA_SxFCR_DMDIS bit
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* - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
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*/
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LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
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/*---------------------------- DMAx SxCR Configuration --------------------------
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* Configure DMAx_Streamy: memory burst transfer with parameters :
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* - MemBurst: DMA_SxCR_MBURST[1:0] bits
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*/
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LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
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/*---------------------------- DMAx SxCR Configuration --------------------------
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* Configure DMAx_Streamy: peripheral burst transfer with parameters :
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* - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
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*/
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LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
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}
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/*-------------------------- DMAx SxM0AR Configuration --------------------------
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* Configure the memory or destination base address with parameter :
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* - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
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*/
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LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
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/*-------------------------- DMAx SxPAR Configuration ---------------------------
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* Configure the peripheral or source base address with parameter :
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* - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
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*/
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LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
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/*--------------------------- DMAx SxNDTR Configuration -------------------------
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* Configure the peripheral base address with parameter :
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* - NbData: DMA_SxNDT[15:0] bits
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*/
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LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
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/*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
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* Configure the peripheral base address with parameter :
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* - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits
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*/
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LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
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return SUCCESS;
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}
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/**
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* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
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* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
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* @retval None
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*/
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void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
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{
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/* Set DMA_InitStruct fields to default values */
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DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
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DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
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DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
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DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
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DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
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DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
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DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
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DMA_InitStruct->NbData = 0x00000000U;
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DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
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DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
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DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
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DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
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DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
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DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* DMA1 || DMA2 */
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/**
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* @}
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*/
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#endif /* USE_FULL_LL_DRIVER */
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