321 lines
6.9 KiB
C
321 lines
6.9 KiB
C
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/*
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* @file adc.c
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* @date Mar 14, 2024
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* @author Francesco Gritti
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*/
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#include "mcu.h"
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#ifdef use_adc
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void ADC_COMP_IRQHandler (void) {
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if ((ADC1->ISR & ADC_ISR_OVR) != 0) {
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ADC1->ISR |= ADC_ISR_OVR; // clear interrupt flag
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ADC1->CR &= ~ADC_CR_ADSTART; // stop ADC
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}
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else if ((ADC1->ISR & ADC_ISR_EOS) != 0) {
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ADC1->ISR |= ADC_ISR_EOS;
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flib_printf ("conv end\n");
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}
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else if ((ADC1->ISR & ADC_ISR_EOC) != 0) {
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ADC1->ISR |= ADC_ISR_EOC;
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u32 adcVal = ADC1->DR;
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flib_printf ("conv\n");
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}
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}
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// NOTE: in case of ADC overrun error, the ADC is stopped and must
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// be re-initalized by clearing OVR flag.
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// when all data requested to the DMA have been transferred, the ADC
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// is automatically stopped
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void ADC_init (void) {
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// enable DMA and ADC clock
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RCC_ADC_CLK_ENABLE();
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// NOTE: must clear ADSTART bit to set some registers
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ADC1->CR = 0x0000;
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ADC1->CFGR2 = (ADC_CLK << ADC_CFGR2_CKMODE_Pos);
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ADC1->CFGR1 = (ADC_CONV_MODE << ADC_CFGR1_CONT_Pos) |
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(ADC_OVRMOD << ADC_CFGR1_OVRMOD_Pos) |
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(ADC_EXTEN_EDGE << ADC_CFGR1_EXTEN_Pos) |
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(ADC_EXTSEL << ADC_CFGR1_EXTSEL_Pos) |
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(ADC_ALIGN_RIGHT << ADC_CFGR1_ALIGN_Pos) |
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(ADC_RES_12bit << ADC_CFGR1_RES_Pos);
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// enable end of sequence and end of conversion interrupt
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ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSIE;
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ADC1->SMPR = (ADC_SAMPLE_TIME << ADC_SMPR_SMP_Pos);
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// enable interrupt
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NVIC_EnableIRQ(ADC1_IRQn);
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NVIC_SetPriority(ADC1_IRQn, 2);
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ADC1->CR |= ADC_CR_ADEN_Msk;
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// wait until ADC is ready for conversion
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u32 startTick = flib_GetTick();
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while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) {
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if((flib_GetTick() - startTick) > 10)
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return;
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}
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}
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void ADC_StartConversion (void) {
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ADC1->CR |= ADC_CR_ADSTART;
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}
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void ADC_addChannelToScanList (u8 channel) {
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ADC1->CHSELR |= (1<<channel);
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}
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void ADC_removeChannelFromScanList (u8 channel) {
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ADC1->CHSELR &= ~(1<<channel);
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}
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// configure DMA and start conversion
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void ADC_startConversionDMA (u8 channels, u16 * ADC_array) {
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DMA1_Channel1->CMAR = (uint32_t)(ADC_array);
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DMA1_Channel1->CNDTR = channels;
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ADC1->CR |= ADC_CR_ADSTART; // start converting and generating DMA requests
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}
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// configure DMA only. Conversion will be triggered lately by software or by hardware
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// through an event
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void ADC_configureDMA (u8 channels, u16 * ADC_array) {
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DMA1_Channel1->CMAR = (uint32_t)(ADC_array);
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DMA1_Channel1->CNDTR = channels;
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}
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u8 ADC_disable (void) {
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ADC1->CR |= ADC_CR_ADDIS_Msk;
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// wait until ADC is actually disabled
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u32 startTick = flib_GetTick();
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while ((ADC1->CR & ADC_CR_ADDIS_Msk) != 0) {
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if((flib_GetTick() - startTick) > 10)
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return 0;
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}
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return 1;
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}
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u8 ADC_enable (void) {
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ADC1->CR |= ADC_CR_ADEN_Msk;
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// wait until ADC is ready for conversion
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u32 startTick = flib_GetTick();
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while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) {
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if((flib_GetTick() - startTick) > 10)
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return 0;
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}
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return 1;
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}
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#endif
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#ifdef use_adc_dma
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__attribute__((weak)) void adc_dma_transferCompleteCallback (void) {
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}
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__attribute__((weak)) void adc_dma_halfTransferCallback (void) {
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}
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void DMA1_CH1_IRQHandler (void) {
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if ((DMA1->ISR & DMA_ISR_GIF1) != 0) {
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// check for transfer complete
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if ((DMA1->ISR & DMA_ISR_TCIF1) != 0) {
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DMA1->IFCR |= DMA_IFCR_CTCIF1;
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DMA1_Channel1->CCR &= ~DMA_CCR_EN; // disable DMA channel
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adc_dma_transferCompleteCallback ();
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}
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// transfer half complete
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else if ((DMA1->ISR & DMA_ISR_HTIF1) != 0) {
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DMA1->IFCR |= DMA_IFCR_CHTIF1;
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adc_dma_halfTransferCallback ();
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}
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// error flag
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else if ((DMA1->ISR & DMA_ISR_TEIF1) != 0) {
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// channel EN bit automatically cleared on DMA error
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// cannot re-enable DMA channel before clearing error flag
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DMA1->IFCR |= DMA_IFCR_CTEIF1;
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// re-init ADC peripheral. Wait for software to call again acquisition
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ADC_init ();
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}
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}
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}
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void ADC_COMP_IRQHandler (void) {
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if ((ADC1->ISR & ADC_ISR_OVR) != 0) {
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ADC1->ISR |= ADC_ISR_OVR; // clear interrupt flag
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ADC1->CR &= ~ADC_CR_ADSTART; // stop ADC
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}
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}
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// NOTE: in case of ADC overrun error, the ADC is stopped and must
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// be re-initalized by clearing OVR flag.
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// when all data requested to the DMA have been transferred, the ADC
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// is automatically stopped
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void ADC_init (void) {
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// enable DMA and ADC clock
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RCC_DMA_CLK_ENABLE();
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RCC_ADC_CLK_ENABLE();
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// NOTE: must clear ADSTART bit to set some registers
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ADC1->CR = 0x0000;
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ADC1->CFGR2 = (ADC_CLK << ADC_CFGR2_CKMODE_Pos);
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ADC1->CFGR1 = (ADC_CONV_MODE << ADC_CFGR1_CONT_Pos) |
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(ADC_OVRMOD << ADC_CFGR1_OVRMOD_Pos) |
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(ADC_EXTEN_EDGE << ADC_CFGR1_EXTEN_Pos) |
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(ADC_EXTSEL << ADC_CFGR1_EXTSEL_Pos) |
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(ADC_ALIGN_RIGHT << ADC_CFGR1_ALIGN_Pos) |
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(ADC_RES_12bit << ADC_CFGR1_RES_Pos) |
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(ADC_DMA_MODE << ADC_CFGR1_DMACFG_Pos) |
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(ADC_DMA_EN << ADC_CFGR1_DMAEN_Pos);
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// disable all interrupt, it will be called by the DMA on transaction completed
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ADC1->IER = 0x00;
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ADC1->SMPR = (ADC_SAMPLE_TIME << ADC_SMPR_SMP_Pos);
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// configure DMA, enabled error, complete interrupts
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DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR));
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DMA1_Channel1->CCR |= DMA_CCR_MINC | (DMA_MSIZE_16_bit << DMA_CCR_MSIZE_Pos) | (DMA_PSIZE_16_bit << DMA_CCR_PSIZE_Pos) |
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DMA_CCR_TEIE | DMA_CCR_TCIE ;
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// enable DMA interrupt needed for errors and transfer complete
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NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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NVIC_SetPriority(DMA1_Channel1_IRQn, 2);
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// enable ADC interrupt needed to detect overrun error and
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// in that case to restart the ADC peripheral
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//NVIC_EnableIRQ(ADC1_IRQn);
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//NVIC_SetPriority(ADC1_IRQn, 2);
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ADC1->CR |= ADC_CR_ADEN_Msk;
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// wait until ADC is ready for conversion
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u32 startTick = flib_GetTick();
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while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) {
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if((flib_GetTick() - startTick) > 10)
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return;
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}
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}
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void ADC_addChannelToScanList (u8 channel) {
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ADC1->CHSELR |= (1<<channel);
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}
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void ADC_removeChannelFromScanList (u8 channel) {
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ADC1->CHSELR &= ~(1<<channel);
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}
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// configure DMA and start conversion
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void ADC_startConversionDMA (u8 channels, u16 * ADC_array) {
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DMA1_Channel1->CCR &= ~DMA_CCR_EN; // disable DMA channel
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DMA1_Channel1->CMAR = (uint32_t)(ADC_array);
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DMA1_Channel1->CNDTR = channels;
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DMA1_Channel1->CCR |= DMA_CCR_EN; // enable DMA
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ADC1->CR |= ADC_CR_ADSTART; // start converting and generating DMA requests
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}
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// configure DMA only. Conversion will be triggered lately by software or by hardware
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// through an event
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void ADC_configureDMA (u8 channels, u16 * ADC_array) {
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DMA1_Channel1->CMAR = (uint32_t)(ADC_array);
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DMA1_Channel1->CNDTR = channels;
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}
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u8 ADC_disable (void) {
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ADC1->CR |= ADC_CR_ADDIS_Msk;
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// wait until ADC is actually disabled
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u32 startTick = flib_GetTick();
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while ((ADC1->CR & ADC_CR_ADDIS_Msk) != 0) {
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if((flib_GetTick() - startTick) > 10)
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return 0;
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}
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return 1;
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}
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u8 ADC_enable (void) {
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ADC1->CR |= ADC_CR_ADEN_Msk;
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// wait until ADC is ready for conversion
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u32 startTick = flib_GetTick();
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while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) {
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if((flib_GetTick() - startTick) > 10)
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return 0;
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}
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return 1;
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}
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#endif
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