129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
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/*
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* tim.h
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*
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* Created on: Apr 3, 2024
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* Author: Francesco Gritti
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*/
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#ifndef TIM_H_
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#define TIM_H_
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/*========================================================================================*
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* TIMER MACROS
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*========================================================================================*/
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typedef enum {
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TIM_OC_ACTIVE_HIGH = 0,
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TIM_OC_ACTIVE_LOW,
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} TIM_OC_ACTIVE_STATE_enum;
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typedef enum {
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TIM_IC_ACTIVE_RISING,
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TIM_IC_ACTIVE_FALLING,
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TIM_IC_ACTIVE_BOTH
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}TIM_IC_ACTIVE_EDGE_enum;
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#define TIM_PWM_MODE1 0x06 // active when CNT < PERIOD
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#define TIM_PWM_MODE2 0x07 // inactive when CNT < PERIOD
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#define TIM_FORCE_ACTIVE 0x05
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#define TIM_FORCE_INACTIVE 0x04
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#define TIM_COUNTER_ENABLE(timer) timer->CR1 |= TIM_CR1_CEN;
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#define TIM_COUNTER_DISABLE(timer) timer->CR1 &= ~TIM_CR1_CEN;
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#define TIM_CH1_ENABLE(tim) tim->CCER |= TIM_CCER_CC1E
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#define TIM_CH2_ENABLE(tim) tim->CCER |= TIM_CCER_CC2E
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#define TIM_CH3_ENABLE(tim) tim->CCER |= TIM_CCER_CC3E
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#define TIM_CH4_ENABLE(tim) tim->CCER |= TIM_CCER_CC4E
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#define TIM_CH1_DISABLE(tim) tim->CCER &= ~TIM_CCER_CC1E
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#define TIM_CH2_DISABLE(tim) tim->CCER &= ~TIM_CCER_CC2E
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#define TIM_CH3_DISABLE(tim) tim->CCER &= ~TIM_CCER_CC3E
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#define TIM_CH4_DISABLE(tim) tim->CCER &= ~TIM_CCER_CC4E
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#define TIM_PWM_SET_CH1_POLARITY_ACTIVE_HIGH(tim) tim->CCER &= ~TIM_CCER_CC1P
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#define TIM_PWM_SET_CH2_POLARITY_ACTIVE_HIGH(tim) tim->CCER &= ~TIM_CCER_CC2P
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#define TIM_PWM_SET_CH3_POLARITY_ACTIVE_HIGH(tim) tim->CCER &= ~TIM_CCER_CC3P
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#define TIM_PWM_SET_CH4_POLARITY_ACTIVE_HIGH(tim) tim->CCER &= ~TIM_CCER_CC4P
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#define TIM_PWM_SET_CH1_POLARITY_ACTIVE_LOW(tim) tim->CCER |= TIM_CCER_CC1P
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#define TIM_PWM_SET_CH2_POLARITY_ACTIVE_LOW(tim) tim->CCER |= TIM_CCER_CC2P
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#define TIM_PWM_SET_CH3_POLARITY_ACTIVE_LOW(tim) tim->CCER |= TIM_CCER_CC3P
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#define TIM_PWM_SET_CH4_POLARITY_ACTIVE_LOW(tim) tim->CCER |= TIM_CCER_CC4P
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#define TIM_SET_COUNTER(tim, counter) tim->CNT = counter
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#define TIM_CH1_SET_COMPARE(tim, cmp) tim->CCR1 = cmp
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#define TIM_CH2_SET_COMPARE(tim, cmp) tim->CCR2 = cmp
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#define TIM_CH3_SET_COMPARE(tim, cmp) tim->CCR3 = cmp
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#define TIM_CH4_SET_COMPARE(tim, cmp) tim->CCR4 = cmp
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#define TIM_CH1_FORCE_ACTIVE(tim) TIM_CH1_SET_OUTCMP_MODE(tim, TIM_FORCE_ACTIVE)
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#define TIM_CH2_FORCE_ACTIVE(tim) TIM_CH2_SET_OUTCMP_MODE(tim, TIM_FORCE_ACTIVE)
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#define TIM_CH3_FORCE_ACTIVE(tim) TIM_CH3_SET_OUTCMP_MODE(tim, TIM_FORCE_ACTIVE)
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#define TIM_CH4_FORCE_ACTIVE(tim) TIM_CH4_SET_OUTCMP_MODE(tim, TIM_FORCE_ACTIVE)
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#define TIM_CH1_FORCE_INACTIVE(tim) TIM_CH1_SET_OUTCMP_MODE(tim, TIM_FORCE_INACTIVE)
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#define TIM_CH2_FORCE_INACTIVE(tim) TIM_CH2_SET_OUTCMP_MODE(tim, TIM_FORCE_INACTIVE)
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#define TIM_CH3_FORCE_INACTIVE(tim) TIM_CH3_SET_OUTCMP_MODE(tim, TIM_FORCE_INACTIVE)
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#define TIM_CH4_FORCE_INACTIVE(tim) TIM_CH4_SET_OUTCMP_MODE(tim, TIM_FORCE_INACTIVE)
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#define TIM_CH1_PWM(tim, mode) TIM_CH1_SET_OUTCMP_MODE(tim, mode)
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#define TIM_CH2_PWM(tim, mode) TIM_CH2_SET_OUTCMP_MODE(tim, mode)
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#define TIM_CH3_PWM(tim, mode) TIM_CH3_SET_OUTCMP_MODE(tim, mode)
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#define TIM_CH4_PWM(tim, mode) TIM_CH4_SET_OUTCMP_MODE(tim, mode)
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#define TIM_CH1_SET_OUTCMP_MODE(tim, mode) \
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{ \
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u32 temp = tim->CCMR1; \
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temp &= ~TIM_CCMR1_OC1M_Msk; \
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temp |= (mode << TIM_CCMR1_OC1M_Pos); \
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tim->CCMR1 = temp; \
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}
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#define TIM_CH2_SET_OUTCMP_MODE(tim, mode) \
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{ \
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u32 temp = tim->CCMR1; \
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temp &= ~TIM_CCMR1_OC2M_Msk; \
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temp |= (mode << TIM_CCMR1_OC2M_Pos); \
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tim->CCMR1 = temp; \
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}
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#define TIM_CH3_SET_OUTCMP_MODE(tim, mode) \
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{ \
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u32 temp = tim->CCMR2; \
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temp &= ~TIM_CCMR2_OC3M_Msk; \
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temp |= (mode << TIM_CCMR2_OC3M_Pos); \
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tim->CCMR2 = temp; \
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}
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#define TIM_CH4_SET_OUTCMP_MODE(tim, mode) \
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{ \
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u32 temp = tim->CCMR2; \
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temp &= ~TIM_CCMR2_OC4M_Msk; \
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temp |= (mode << TIM_CCMR2_OC4M_Pos); \
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tim->CCMR2 = temp; \
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}
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#endif /* TIM_H_ */
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