/*
 * tim.h
 *
 * Created on: Apr 3, 2024
 * Author: Francesco Gritti
 */

#ifndef TIM_H_
#define TIM_H_




/*========================================================================================*
 *                                    TIMER MACROS
 *========================================================================================*/


typedef enum {

	TIM_OC_ACTIVE_HIGH = 0,
	TIM_OC_ACTIVE_LOW,
} TIM_OC_ACTIVE_STATE_enum;

typedef enum {

	TIM_IC_ACTIVE_RISING,
	TIM_IC_ACTIVE_FALLING,
	TIM_IC_ACTIVE_BOTH

}TIM_IC_ACTIVE_EDGE_enum;





#define TIM_PWM_MODE1		0x06			// active   when CNT < PERIOD
#define TIM_PWM_MODE2		0x07			// inactive when CNT < PERIOD
#define TIM_FORCE_ACTIVE	0x05
#define TIM_FORCE_INACTIVE	0x04


#define TIM_COUNTER_ENABLE(timer)		timer->CR1 |= TIM_CR1_CEN;
#define TIM_COUNTER_DISABLE(timer)		timer->CR1 &= ~TIM_CR1_CEN;

#define TIM_CH1_ENABLE(tim)			tim->CCER |= TIM_CCER_CC1E
#define TIM_CH2_ENABLE(tim)			tim->CCER |= TIM_CCER_CC2E
#define TIM_CH3_ENABLE(tim)			tim->CCER |= TIM_CCER_CC3E
#define TIM_CH4_ENABLE(tim)			tim->CCER |= TIM_CCER_CC4E

#define TIM_CH1_DISABLE(tim)		tim->CCER &= ~TIM_CCER_CC1E
#define TIM_CH2_DISABLE(tim)		tim->CCER &= ~TIM_CCER_CC2E
#define TIM_CH3_DISABLE(tim)		tim->CCER &= ~TIM_CCER_CC3E
#define TIM_CH4_DISABLE(tim)		tim->CCER &= ~TIM_CCER_CC4E

#define TIM_PWM_SET_CH1_POLARITY_ACTIVE_HIGH(tim)	tim->CCER &= ~TIM_CCER_CC1P
#define TIM_PWM_SET_CH2_POLARITY_ACTIVE_HIGH(tim)	tim->CCER &= ~TIM_CCER_CC2P
#define TIM_PWM_SET_CH3_POLARITY_ACTIVE_HIGH(tim)	tim->CCER &= ~TIM_CCER_CC3P
#define TIM_PWM_SET_CH4_POLARITY_ACTIVE_HIGH(tim)	tim->CCER &= ~TIM_CCER_CC4P

#define TIM_PWM_SET_CH1_POLARITY_ACTIVE_LOW(tim)	tim->CCER |= TIM_CCER_CC1P
#define TIM_PWM_SET_CH2_POLARITY_ACTIVE_LOW(tim)	tim->CCER |= TIM_CCER_CC2P
#define TIM_PWM_SET_CH3_POLARITY_ACTIVE_LOW(tim)	tim->CCER |= TIM_CCER_CC3P
#define TIM_PWM_SET_CH4_POLARITY_ACTIVE_LOW(tim)	tim->CCER |= TIM_CCER_CC4P

#define TIM_SET_COUNTER(tim, counter)				tim->CNT = counter

#define TIM_CH1_SET_COMPARE(tim, cmp)		tim->CCR1 = cmp
#define TIM_CH2_SET_COMPARE(tim, cmp)		tim->CCR2 = cmp
#define TIM_CH3_SET_COMPARE(tim, cmp)		tim->CCR3 = cmp
#define TIM_CH4_SET_COMPARE(tim, cmp)		tim->CCR4 = cmp


#define TIM_CH1_FORCE_ACTIVE(tim)		TIM_CH1_SET_OUTCMP_MODE(tim, TIM_FORCE_ACTIVE)
#define TIM_CH2_FORCE_ACTIVE(tim)		TIM_CH2_SET_OUTCMP_MODE(tim, TIM_FORCE_ACTIVE)
#define TIM_CH3_FORCE_ACTIVE(tim)		TIM_CH3_SET_OUTCMP_MODE(tim, TIM_FORCE_ACTIVE)
#define TIM_CH4_FORCE_ACTIVE(tim)		TIM_CH4_SET_OUTCMP_MODE(tim, TIM_FORCE_ACTIVE)

#define TIM_CH1_FORCE_INACTIVE(tim)		TIM_CH1_SET_OUTCMP_MODE(tim, TIM_FORCE_INACTIVE)
#define TIM_CH2_FORCE_INACTIVE(tim)		TIM_CH2_SET_OUTCMP_MODE(tim, TIM_FORCE_INACTIVE)
#define TIM_CH3_FORCE_INACTIVE(tim)		TIM_CH3_SET_OUTCMP_MODE(tim, TIM_FORCE_INACTIVE)
#define TIM_CH4_FORCE_INACTIVE(tim)		TIM_CH4_SET_OUTCMP_MODE(tim, TIM_FORCE_INACTIVE)

#define TIM_CH1_PWM(tim, mode)			TIM_CH1_SET_OUTCMP_MODE(tim, mode)
#define TIM_CH2_PWM(tim, mode)			TIM_CH2_SET_OUTCMP_MODE(tim, mode)
#define TIM_CH3_PWM(tim, mode)			TIM_CH3_SET_OUTCMP_MODE(tim, mode)
#define TIM_CH4_PWM(tim, mode)			TIM_CH4_SET_OUTCMP_MODE(tim, mode)



#define TIM_CH1_SET_OUTCMP_MODE(tim, mode)		\
{												\
	u32 temp = tim->CCMR1;						\
	temp &= ~TIM_CCMR1_OC1M_Msk;				\
	temp |= (mode << TIM_CCMR1_OC1M_Pos);		\
	tim->CCMR1 = temp;							\
}


#define TIM_CH2_SET_OUTCMP_MODE(tim, mode)		\
{												\
	u32 temp = tim->CCMR1;						\
	temp &= ~TIM_CCMR1_OC2M_Msk;				\
	temp |= (mode << TIM_CCMR1_OC2M_Pos);		\
	tim->CCMR1 = temp;							\
}

#define TIM_CH3_SET_OUTCMP_MODE(tim, mode)		\
{												\
	u32 temp = tim->CCMR2;						\
	temp &= ~TIM_CCMR2_OC3M_Msk;				\
	temp |= (mode << TIM_CCMR2_OC3M_Pos);		\
	tim->CCMR2 = temp;							\
}

#define TIM_CH4_SET_OUTCMP_MODE(tim, mode)		\
{												\
	u32 temp = tim->CCMR2;						\
	temp &= ~TIM_CCMR2_OC4M_Msk;				\
	temp |= (mode << TIM_CCMR2_OC4M_Pos);		\
	tim->CCMR2 = temp;							\
}





#endif /* TIM_H_ */