434 lines
10 KiB
C
434 lines
10 KiB
C
/* **************************************************************************
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* @file mcu.h
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*
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* @date March 6 2024
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* @author Francesco Gritti
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****************************************************************************
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*
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*
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*
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*
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*/
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#ifndef MCU_h
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#define MCU_h
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#include "ftypes.h"
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#include "stm32f042x6.h"
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#include "main.h"
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u32 getTick (void);
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#define flib_GetTick getTick
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typedef struct {
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u32 SYS_clk;
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u32 sysTick_clk;
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u32 APB_clk;
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u32 AHB_clk;
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u32 TIM_clk;
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u32 USART1_clk;
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u32 USART2_clk;
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u32 USART3_clk;
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u32 ADC_clk;
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}systemClockTreeT;
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extern volatile systemClockTreeT systemClockTree;
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/*========================================================================================*
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* DRIVER CONFIGURATION
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*========================================================================================*/
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#include "gpio.h"
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#include "tim.h"
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#if defined(tim1_timebase)
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void TIM1_init (void);
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#endif
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#if defined(tim2_pwm)
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void TIM2_pwm_init (void);
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void TIM2_pwm_config_ch1 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
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void TIM2_pwm_config_ch2 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
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void TIM2_pwm_config_ch3 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
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void TIM2_pwm_config_ch4 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
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#elif defined (tim2_ic) || defined (tim2_adc_timebase)
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void TIM2_init (void);
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#endif
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#if defined(tim3_pwm)
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void TIM3_pwm_init (void);
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void TIM3_pwm_config_ch1 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
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void TIM3_pwm_config_ch2 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
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void TIM3_pwm_config_ch3 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
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void TIM3_pwm_config_ch4 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
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#elif defined (tim3_ic)
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void TIM3_ic_init (void);
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#elif defined (tim3_adc_timebase)
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void TIM3_init (void);
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#endif
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#if defined(tim14_timer)
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void TIM14_init (void);
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#endif
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#if defined(use_can)
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#include "can.h"
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#endif
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#if defined(use_usart1)
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#include "usart1.h"
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#endif
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/*========================================================================================*
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* CLOCK DEFINITIONS, MACROS AND FUNCTIONS
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*========================================================================================*/
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// clock configuration must be specified in "main.h" since it can be
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// custom for every application
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void clock_init (void);
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void backup_clock_init (void);
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typedef enum {
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PLL_MUL_2 = 0,
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PLL_MUL_3,
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PLL_MUL_4,
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PLL_MUL_5,
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PLL_MUL_6,
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PLL_MUL_7,
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PLL_MUL_8,
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PLL_MUL_9,
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PLL_MUL_10,
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PLL_MUL_11,
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PLL_MUL_12,
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PLL_MUL_13,
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PLL_MUL_14,
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PLL_MUL_15,
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PLL_MUL_16,
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}pll_mul;
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typedef enum {
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SYSCLK_SRC_HSI = 0,
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SYSCLK_SRC_HSE,
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SYSCLK_SRC_PLL,
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SYSCLK_SRC_HSI48,
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}sysclk_src;
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typedef enum {
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PLL_SRC_HSI_2 = 0,
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PLL_SRC_HSI_PREDIV,
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PLL_SRC_HSE_PREDIV,
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PLL_SRC_HSI48_PREDIV,
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}pll_src;
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typedef enum {
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AHB_SRC_SYSCLK = 0,
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AHB_SRC_SYSCLK_2 = 8,
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AHB_SRC_SYSCLK_4,
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AHB_SRC_SYSCLK_8,
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AHB_SRC_SYSCLK_16,
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AHB_SRC_SYSCLK_64,
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AHB_SRC_SYSCLK_128,
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AHB_SRC_SYSCLK_256,
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AHB_SRC_SYSCLK_512,
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}ahb_clk_src;
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typedef enum {
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APB_SRC_AHB = 0,
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APB_SRC_AHB_2 = 4,
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APB_SRC_AHB_4,
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APB_SRC_AHB_8,
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APB_SRC_AHB_16
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}apb_clk_src;
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typedef enum {
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CSS_DISABLE,
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CSS_ENABLE
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}clock_security_system;
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// this macro allows to correctly enable one peripheral's clock.
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// after setting the relative bit, it reads back the value
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// effectively delaying two clock cycles (cause of the &
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// operation. The compiler is prevented from optimizing
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// this operation away by declaring tmpreg as volatile
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#define ENABLE_CLK(reg, bit) do { \
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volatile u32 tmpreg; \
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reg |= bit; \
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = (RCC->APB1ENR & RCC_APB1ENR_CANEN); \
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(void) tmpreg; \
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} while(0U)
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#define FLASH_PREFATCH_ENABLE() FLASH->ACR |= FLASH_ACR_PRFTBE
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#define SYSCFG_REMAP_PA11_PA12() SYSCFG->CFGR1 |= SYSCFG_CFGR1_PA11_PA12_RMP
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#define SYSCFG_REMAP_SRAM() SYSCFG->CFGR1 |= 0b11;
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#define SYSCFG_REMAP_FLASH() SYSCFG->CFGR1 &= ~0b11;
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#define SYSCFG_DISABLE_REMAP_PA11_PA12() SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_PA11_PA12_RMP
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#define RCC_TIM1_CLK_ENABLE() ENABLE_CLK(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
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#define RCC_TIM2_CLK_ENABLE() ENABLE_CLK(RCC->APB1ENR, RCC_APB1ENR_TIM2EN)
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#define RCC_TIM3_CLK_ENABLE() ENABLE_CLK(RCC->APB1ENR, RCC_APB1ENR_TIM3EN)
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#define RCC_TIM14_CLK_ENABLE() ENABLE_CLK(RCC->APB1ENR, RCC_APB1ENR_TIM14EN)
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#define RCC_USART1_CLK_ENABLE() ENABLE_CLK(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
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#define RCC_GPIOA_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIOAEN)
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#define RCC_GPIOB_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIOBEN)
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#define RCC_GPIOC_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIOCEN)
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#define RCC_GPIOD_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIODEN)
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#define RCC_GPIOE_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIOEEN)
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#define RCC_GPIOF_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIOFEN)
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#define RCC_CAN1_CLK_ENABLE() ENABLE_CLK(RCC->APB1ENR, RCC_APB1ENR_CANEN)
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#define RCC_SYSCFG_CLK_ENABLE() ENABLE_CLK(RCC->APB2ENR, RCC_APB2ENR_SYSCFGCOMPEN)
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#define RCC_PWR_CLK_ENABLE() ENABLE_CLK(RCC->APB1ENR, RCC_APB1ENR_PWREN)
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#define RCC_DMA_CLK_ENABLE() ENABLE_CLK (RCC->AHBENR, RCC_AHBENR_DMAEN)
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#define RCC_ADC_CLK_ENABLE() ENABLE_CLK (RCC->APB2ENR, RCC_APB2ENR_ADCEN)
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/*========================================================================================*
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* USART MACROS
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*========================================================================================*/
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#define USART_TX_ENABLE(usart) (usart->CR1 |= USART_CR1_TE)
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#define USART_TX_DISABLE(usart) (usart->CR1 &= ~USART_CR1_TE)
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#define USART_RX_ENABLE(usart) (usart->CR1 |= USART_CR1_RE)
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#define USART_RX_DISABLE(usart) (usart->CR1 &= ~USART_CR1_RE)
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#define USART_ENABLE(usart) (usart->CR1 |= USART_CR1_UE)
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#define USART_DISABLE(usart) (usart->CR1 &= ~USART_CR1_UE)
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// enable usart, receiver and transmitter
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#define USART_START(usart) (usart->CR1 |= (USART_CR1_RE | USART_CR1_TE | USART_CR1_UE))
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#define USART_STOP(usart) (usart->CR1 &= ~(USART_CR1_RE | USART_CR1_TE | USART_CR1_UE))
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#define USART_ENABLE_TX_DATA_REGISTER_EMPTY_INT(usart) (usart->CR1 |= USART_CR1_TXEIE)
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#define USART_DISABLE_TX_DATA_REGISTER_EMPTY_INT(usart) (usart->CR1 &= ~USART_CR1_TXEIE)
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#define USART_ENABLE_DATA_RECEIVED_INT(usart) (usart->CR1 |= USART_CR1_RXNEIE)
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#define USART_DISABLE_DATA_RECEIVED_INT(usart) (usart->CR1 &= ~USART_CR1_RXNEIE)
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#define USART_SET_TRANSMIT_DATA(usart, data) (usart->TDR = data)
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/*========================================================================================*
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* ADC MACROS
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*========================================================================================*/
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typedef enum {
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ADC_CONV_MODE_SINGLE = 0,
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ADC_CONV_MODE_CONTINUOUS
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}adc_conv_mode;
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typedef enum {
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ADC_OVRMOD_PRESERVE = 0,
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ADC_OVRMOD_OVERWRITE
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}adc_ovrmod;
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typedef enum {
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ADC_EXTEN_DISABLED = 0,
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ADC_EXTEN_RISING_EDGE,
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ADC_EXTEN_FALLING_EDGE,
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ADC_EXTEN_BOTH_EDGES
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}adc_ext_trig_en;
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typedef enum {
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ADC_EXTSEL_TIM1_TRGO = 0,
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ADC_EXTSEL_TIM1_CC4,
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ADC_EXTSEL_TIM2_TRGO,
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ADC_EXTSEL_TIM3_TRGO,
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ADC_EXTSEL_TIM15_TRGO,
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}adc_extsel;
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typedef enum {
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ADC_ALIGN_RIGHT = 0,
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ADC_ALIGN_LEFT
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}adc_align;
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typedef enum {
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ADC_RES_12bit = 0,
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ADC_RES_10bit,
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ADC_RES_8bit,
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ADC_RES_6bit
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}adc_resolution;
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typedef enum {
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ADC_DMA_MODE_ONE_SHOT = 0,
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ADC_DMA_MODE_CIRCULAR
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}adc_dma_mode;
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typedef enum {
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ADC_DMA_DISABLED = 0,
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ADC_DMA_ENABLED
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}adc_dma_enable;
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typedef enum {
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ADC_CLK_ADCCLK = 0,
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ADC_CLK_PCLK_2,
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ADC_CLK_PCLK_4,
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}adc_clk;
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typedef enum {
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ADC_SAMPLE_TIME_1_5 = 0,
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ADC_SAMPLE_TIME_7_5,
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ADC_SAMPLE_TIME_13_5,
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ADC_SAMPLE_TIME_28_5,
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ADC_SAMPLE_TIME_41_5,
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ADC_SAMPLE_TIME_55_5,
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ADC_SAMPLE_TIME_71_5,
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ADC_SAMPLE_TIME_239_5,
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}adc_sample_time;
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#define ADC_CHANNEL_0 ( 0x00000000U)
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#define ADC_CHANNEL_1 ( 0x00000001U)
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#define ADC_CHANNEL_2 ( 0x00000002U)
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#define ADC_CHANNEL_3 ( 0x00000003U)
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#define ADC_CHANNEL_4 ( 0x00000004U)
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#define ADC_CHANNEL_5 ( 0x00000005U)
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#define ADC_CHANNEL_6 ( 0x00000006U)
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#define ADC_CHANNEL_7 ( 0x00000007U)
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#define ADC_CHANNEL_8 ( 0x00000008U)
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#define ADC_CHANNEL_9 ( 0x00000009U)
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#define ADC_CHANNEL_10 ( 0x0000000AU)
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#define ADC_CHANNEL_11 ( 0x0000000BU)
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#define ADC_CHANNEL_12 ( 0x0000000CU)
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#define ADC_CHANNEL_13 ( 0x0000000DU)
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#define ADC_CHANNEL_14 ( 0x0000000EU)
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#define ADC_CHANNEL_15 ( 0x0000000FU)
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#define ADC_CHANNEL_16 ( 0x00000010U)
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#define ADC_CHANNEL_17 ( 0x00000011U)
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#if defined(use_adc) || defined(use_adc_dma)
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void ADC_init (void);
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void ADC_addChannelToScanList (u8 channel);
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void ADC_removeChannelFromScanList (u8 channel);
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// configure DMA and start conversion
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void ADC_startConversionDMA (u8 channels, u16 * ADC_array);
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// configure DMA only. Conversion will be triggered lately by software or by hardware
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// through an event
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void ADC_configureDMA (u8 channels, u16 * ADC_array);
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u8 ADC_disable (void);
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u8 ADC_enable (void);
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#endif
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/*========================================================================================*
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* DMA MACROS
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*========================================================================================*/
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typedef enum {
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DMA_MSIZE_8_bit = 0,
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DMA_MSIZE_16_bit,
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DMA_MSIZE_32_bit
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}dma_msize;
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typedef enum {
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DMA_PSIZE_8_bit = 0,
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DMA_PSIZE_16_bit,
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DMA_PSIZE_32_bit
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}dma_psize;
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typedef enum {
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DMA_PRIO_LOW = 0,
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DMA_PRIO_MEDIUM,
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DMA_PRIO_HIGH,
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DMA_PRIO_VERY_HIGH,
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}dma_prio;
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#define DMA_SET_NDATA(dma_channel, n) dma_channel->NDT = n
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/*========================================================================================*
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* CRC
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*========================================================================================*/
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void crc_reset (void);
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u32 crc_compute (u32* start_address, u32* end_address);
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u32 crc_get (void);
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#endif /* MCU_h */
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