195 lines
4.0 KiB
C
195 lines
4.0 KiB
C
/*
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* tim2.c
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*
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* Created on: Dec 30, 2023
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* Author: Francesco Gritti
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*
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* This file contains implementation of booth timer 2 input capture and PWM
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* generation features. only one of the two features can be enabled by
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* defining the macros "tim2_pwm" or "tim2_ic".
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*
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* GPIOs connected to the input/output channels of the timer should be
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* defined in main.h and they are initialized into the TIM2_init function
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*/
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#include "main.h"
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#include "mcu.h"
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#ifdef tim2_adc_timebase
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void TIM2_init (void) {
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RCC_TIM2_CLK_ENABLE();
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TIM2->CR1 = 0x0000;
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TIM2->CR2 = (0b010 << TIM_CR2_MMS_Pos);
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TIM2->DIER = 0x0000; // disable all interrupt requests
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TIM2->PSC = TIM2_PSC;
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TIM2->ARR = TIM2_PERIOD;
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TIM2->CR1 |= TIM_CR1_CEN;
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}
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#endif
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#ifdef tim2_pwm
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void TIM2_pwm_config_ch1 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value) {
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TIM2->CCMR1 = (TIM_FORCE_INACTIVE << TIM_CCMR1_OC1M_Pos) | TIM_CCMR1_OC1PE;
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if (activeState == TIM_OC_ACTIVE_HIGH)
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TIM_PWM_SET_CH1_POLARITY_ACTIVE_HIGH (TIM2);
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else
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TIM_PWM_SET_CH1_POLARITY_ACTIVE_LOW (TIM2);
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TIM2->CCR1 = value;
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TIM_CH1_FORCE_INACTIVE(TIM2);
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TIM_CH1_ENABLE(TIM2);
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}
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void TIM2_pwm_config_ch2 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value) {
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TIM2->CCMR1 = (TIM_FORCE_INACTIVE << TIM_CCMR1_OC2M_Pos) | TIM_CCMR1_OC2PE;
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if (activeState == TIM_OC_ACTIVE_HIGH)
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TIM_PWM_SET_CH2_POLARITY_ACTIVE_HIGH (TIM2);
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else
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TIM_PWM_SET_CH2_POLARITY_ACTIVE_LOW (TIM2);
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TIM2->CCR2 = value;
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TIM_CH2_FORCE_INACTIVE(TIM2);
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TIM_CH2_ENABLE(TIM2);
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}
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void TIM2_pwm_config_ch3 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value) {
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TIM2->CCMR2 = (TIM_FORCE_INACTIVE << TIM_CCMR2_OC3M_Pos) | TIM_CCMR2_OC3PE;
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if (activeState == TIM_OC_ACTIVE_HIGH)
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TIM_PWM_SET_CH3_POLARITY_ACTIVE_HIGH (TIM2);
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else
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TIM_PWM_SET_CH3_POLARITY_ACTIVE_LOW (TIM2);
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TIM2->CCR3 = value;
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TIM_CH3_ENABLE(TIM2);
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}
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void TIM2_pwm_config_ch4 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value) {
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TIM2->CCMR2 = (TIM_FORCE_INACTIVE << TIM_CCMR2_OC4M_Pos) | TIM_CCMR2_OC4PE;
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if (activeState == TIM_OC_ACTIVE_HIGH)
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TIM_PWM_SET_CH4_POLARITY_ACTIVE_HIGH (TIM2);
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else
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TIM_PWM_SET_CH4_POLARITY_ACTIVE_LOW (TIM2);
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TIM2->CCR4 = value;
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TIM_CH4_ENABLE(TIM2);
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}
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void TIM2_pwm_init (void) {
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RCC_TIM2_CLK_ENABLE ();
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TIM2->CR1 = 0x0000;
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TIM2->CR2 = 0x0000;
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TIM2->SMCR = 0x0000;
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TIM2->DIER = 0x0000;
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// disable all channels
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TIM2->CCER = 0x0000;
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// force CH1 and CH2 inactive, enable compare PRELOAD
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TIM2->CCMR1 = 0x0000;
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TIM2->CCMR2 = 0x0000;
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// reset counter
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TIM2->CNT = 0x0000;
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//set PRESCALER
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TIM2->PSC = TIM2_PSC;
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// set PERIOD
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TIM2->ARR = TIM2_PERIOD;
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// reset all PWM periods
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TIM2->CCR1 = 0x0000;
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TIM2->CCR2 = 0x0000;
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TIM2->CCR3 = 0x0000;
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TIM2->CCR4 = 0x0000;
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TIM_COUNTER_ENABLE (TIM2);
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}
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/*GPIO_AF_PP (TIM2_PWM_CH1);
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GPIO_AF_PP (TIM2_PWM_CH2);
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GPIO_AF_PP (TIM2_PWM_CH3);
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GPIO_AF_PP (TIM2_PWM_CH4);
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GPIO_SET_AFRL (TIM2_PWM_CH1, GPIO_AF_TIM2);
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GPIO_SET_AFRL (TIM2_PWM_CH2, GPIO_AF_TIM2);
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GPIO_SET_AFRL (TIM2_PWM_CH3, GPIO_AF_TIM2);
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GPIO_SET_AFRL (TIM2_PWM_CH4, GPIO_AF_TIM2);*/
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#elif defined(tim2_ic)
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void TIM2_init(void) {
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RCC_TIM2_CLK_ENABLE();
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RCC_GPIOA_CLK_ENABLE();
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/* =============== configure GPIO ================*/
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GPIO_AF_PP (TIM2_IN_CH2);
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GPIO_SET_AFRL (TIM2_IN_CH2, 0x02);
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/* ====== configure timer capture channels ======*/
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// configure channel 2 as input capture with filter 3
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TIM2->CCMR1 = (3 << TIM_CCMR1_IC2F_Pos) | (0b01 << TIM_CCMR1_CC2S_Pos);
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// capture on falling edge only, enable channel
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TIM2->CCER = TIM_CCER_CC2P | TIM_CCER_CC2E;
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/* Configure base timer */
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// enable interrupt on timer update and on channel2 input capture
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TIM2->DIER = TIM_DIER_UIE | TIM_DIER_CC2IE;
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TIM2->PSC = TIM2_PSC; // 54;
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TIM2->ARR = TIM2_PERIOD; // 65535;
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// request UEV event only on underflow/overflow and enable timer
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TIM2->CR1 = TIM_CR1_URS | TIM_CR1_CEN;
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// set highest priority since the handler is a non blocking function
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NVIC_SetPriority(TIM2_IRQn, 0);
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NVIC_EnableIRQ(TIM2_IRQn);
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}
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__attribute__ ((weak)) void TIM2_IRQHandler (void) {
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// clear IT flag
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}
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#endif
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