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STM32F042-Drivers-Pub/mcu.h

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2024-05-02 10:18:04 +00:00
/* **************************************************************************
* @file mcu.h
*
* @date March 6 2024
* @author Francesco Gritti
****************************************************************************
*
*
*
*
*/
#ifndef MCU_h
#define MCU_h
#include "ftypes.h"
#include "stm32f042x6.h"
#include "main.h"
u32 getTick (void);
#define flib_GetTick getTick
typedef struct {
u32 SYS_clk;
u32 sysTick_clk;
u32 APB_clk;
u32 AHB_clk;
u32 TIM_clk;
u32 USART1_clk;
u32 USART2_clk;
u32 USART3_clk;
u32 ADC_clk;
}systemClockTreeT;
extern volatile systemClockTreeT systemClockTree;
/*========================================================================================*
* DRIVER CONFIGURATION
*========================================================================================*/
#include "gpio.h"
#include "tim.h"
#if defined(tim1_timebase)
void TIM1_init (void);
#endif
#if defined(tim2_pwm)
void TIM2_pwm_init (void);
void TIM2_pwm_config_ch1 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
void TIM2_pwm_config_ch2 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
void TIM2_pwm_config_ch3 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
void TIM2_pwm_config_ch4 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
#elif defined (tim2_ic) || defined (tim2_adc_timebase)
void TIM2_init (void);
#endif
#if defined(tim3_pwm)
void TIM3_pwm_init (void);
void TIM3_pwm_config_ch1 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
void TIM3_pwm_config_ch2 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
void TIM3_pwm_config_ch3 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
void TIM3_pwm_config_ch4 (TIM_OC_ACTIVE_STATE_enum activeState, u16 value);
#elif defined (tim3_ic)
void TIM3_ic_init (void);
#elif defined (tim3_adc_timebase)
void TIM3_init (void);
#endif
#if defined(tim14_timer)
void TIM14_init (void);
#endif
#if defined(use_can)
#include "can.h"
#endif
#if defined(use_usart1)
#include "usart1.h"
#endif
/*========================================================================================*
* CLOCK DEFINITIONS, MACROS AND FUNCTIONS
*========================================================================================*/
// clock configuration must be specified in "main.h" since it can be
// custom for every application
void clock_init (void);
void backup_clock_init (void);
typedef enum {
PLL_MUL_2 = 0,
PLL_MUL_3,
PLL_MUL_4,
PLL_MUL_5,
PLL_MUL_6,
PLL_MUL_7,
PLL_MUL_8,
PLL_MUL_9,
PLL_MUL_10,
PLL_MUL_11,
PLL_MUL_12,
PLL_MUL_13,
PLL_MUL_14,
PLL_MUL_15,
PLL_MUL_16,
}pll_mul;
typedef enum {
SYSCLK_SRC_HSI = 0,
SYSCLK_SRC_HSE,
SYSCLK_SRC_PLL,
SYSCLK_SRC_HSI48,
}sysclk_src;
typedef enum {
PLL_SRC_HSI_2 = 0,
PLL_SRC_HSI_PREDIV,
PLL_SRC_HSE_PREDIV,
PLL_SRC_HSI48_PREDIV,
}pll_src;
typedef enum {
AHB_SRC_SYSCLK = 0,
AHB_SRC_SYSCLK_2 = 8,
AHB_SRC_SYSCLK_4,
AHB_SRC_SYSCLK_8,
AHB_SRC_SYSCLK_16,
AHB_SRC_SYSCLK_64,
AHB_SRC_SYSCLK_128,
AHB_SRC_SYSCLK_256,
AHB_SRC_SYSCLK_512,
}ahb_clk_src;
typedef enum {
APB_SRC_AHB = 0,
APB_SRC_AHB_2 = 4,
APB_SRC_AHB_4,
APB_SRC_AHB_8,
APB_SRC_AHB_16
}apb_clk_src;
typedef enum {
CSS_DISABLE,
CSS_ENABLE
}clock_security_system;
// this macro allows to correctly enable one peripheral's clock.
// after setting the relative bit, it reads back the value
// effectively delaying two clock cycles (cause of the &
// operation. The compiler is prevented from optimizing
// this operation away by declaring tmpreg as volatile
#define ENABLE_CLK(reg, bit) do { \
volatile u32 tmpreg; \
reg |= bit; \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = (RCC->APB1ENR & RCC_APB1ENR_CANEN); \
(void) tmpreg; \
} while(0U)
#define FLASH_PREFATCH_ENABLE() FLASH->ACR |= FLASH_ACR_PRFTBE
#define SYSCFG_REMAP_PA11_PA12() SYSCFG->CFGR1 |= SYSCFG_CFGR1_PA11_PA12_RMP
#define SYSCFG_REMAP_SRAM() SYSCFG->CFGR1 |= 0b11;
#define SYSCFG_REMAP_FLASH() SYSCFG->CFGR1 &= ~0b11;
#define SYSCFG_DISABLE_REMAP_PA11_PA12() SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_PA11_PA12_RMP
#define RCC_TIM1_CLK_ENABLE() ENABLE_CLK(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
#define RCC_TIM2_CLK_ENABLE() ENABLE_CLK(RCC->APB1ENR, RCC_APB1ENR_TIM2EN)
#define RCC_TIM3_CLK_ENABLE() ENABLE_CLK(RCC->APB1ENR, RCC_APB1ENR_TIM3EN)
#define RCC_TIM14_CLK_ENABLE() ENABLE_CLK(RCC->APB1ENR, RCC_APB1ENR_TIM14EN)
#define RCC_USART1_CLK_ENABLE() ENABLE_CLK(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
#define RCC_GPIOA_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIOAEN)
#define RCC_GPIOB_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIOBEN)
#define RCC_GPIOC_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIOCEN)
#define RCC_GPIOD_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIODEN)
#define RCC_GPIOE_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIOEEN)
#define RCC_GPIOF_CLK_ENABLE() ENABLE_CLK(RCC->AHBENR, RCC_AHBENR_GPIOFEN)
#define RCC_CAN1_CLK_ENABLE() ENABLE_CLK(RCC->APB1ENR, RCC_APB1ENR_CANEN)
#define RCC_SYSCFG_CLK_ENABLE() ENABLE_CLK(RCC->APB2ENR, RCC_APB2ENR_SYSCFGCOMPEN)
#define RCC_PWR_CLK_ENABLE() ENABLE_CLK(RCC->APB1ENR, RCC_APB1ENR_PWREN)
#define RCC_DMA_CLK_ENABLE() ENABLE_CLK (RCC->AHBENR, RCC_AHBENR_DMAEN)
#define RCC_ADC_CLK_ENABLE() ENABLE_CLK (RCC->APB2ENR, RCC_APB2ENR_ADCEN)
/*========================================================================================*
* USART MACROS
*========================================================================================*/
#define USART_TX_ENABLE(usart) (usart->CR1 |= USART_CR1_TE)
#define USART_TX_DISABLE(usart) (usart->CR1 &= ~USART_CR1_TE)
#define USART_RX_ENABLE(usart) (usart->CR1 |= USART_CR1_RE)
#define USART_RX_DISABLE(usart) (usart->CR1 &= ~USART_CR1_RE)
#define USART_ENABLE(usart) (usart->CR1 |= USART_CR1_UE)
#define USART_DISABLE(usart) (usart->CR1 &= ~USART_CR1_UE)
// enable usart, receiver and transmitter
#define USART_START(usart) (usart->CR1 |= (USART_CR1_RE | USART_CR1_TE | USART_CR1_UE))
#define USART_STOP(usart) (usart->CR1 &= ~(USART_CR1_RE | USART_CR1_TE | USART_CR1_UE))
#define USART_ENABLE_TX_DATA_REGISTER_EMPTY_INT(usart) (usart->CR1 |= USART_CR1_TXEIE)
#define USART_DISABLE_TX_DATA_REGISTER_EMPTY_INT(usart) (usart->CR1 &= ~USART_CR1_TXEIE)
#define USART_ENABLE_DATA_RECEIVED_INT(usart) (usart->CR1 |= USART_CR1_RXNEIE)
#define USART_DISABLE_DATA_RECEIVED_INT(usart) (usart->CR1 &= ~USART_CR1_RXNEIE)
#define USART_SET_TRANSMIT_DATA(usart, data) (usart->TDR = data)
/*========================================================================================*
* ADC MACROS
*========================================================================================*/
typedef enum {
ADC_CONV_MODE_SINGLE = 0,
ADC_CONV_MODE_CONTINUOUS
}adc_conv_mode;
typedef enum {
ADC_OVRMOD_PRESERVE = 0,
ADC_OVRMOD_OVERWRITE
}adc_ovrmod;
typedef enum {
ADC_EXTEN_DISABLED = 0,
ADC_EXTEN_RISING_EDGE,
ADC_EXTEN_FALLING_EDGE,
ADC_EXTEN_BOTH_EDGES
}adc_ext_trig_en;
typedef enum {
ADC_EXTSEL_TIM1_TRGO = 0,
ADC_EXTSEL_TIM1_CC4,
ADC_EXTSEL_TIM2_TRGO,
ADC_EXTSEL_TIM3_TRGO,
ADC_EXTSEL_TIM15_TRGO,
}adc_extsel;
typedef enum {
ADC_ALIGN_RIGHT = 0,
ADC_ALIGN_LEFT
}adc_align;
typedef enum {
ADC_RES_12bit = 0,
ADC_RES_10bit,
ADC_RES_8bit,
ADC_RES_6bit
}adc_resolution;
typedef enum {
ADC_DMA_MODE_ONE_SHOT = 0,
ADC_DMA_MODE_CIRCULAR
}adc_dma_mode;
typedef enum {
ADC_DMA_DISABLED = 0,
ADC_DMA_ENABLED
}adc_dma_enable;
typedef enum {
ADC_CLK_ADCCLK = 0,
ADC_CLK_PCLK_2,
ADC_CLK_PCLK_4,
}adc_clk;
typedef enum {
ADC_SAMPLE_TIME_1_5 = 0,
ADC_SAMPLE_TIME_7_5,
ADC_SAMPLE_TIME_13_5,
ADC_SAMPLE_TIME_28_5,
ADC_SAMPLE_TIME_41_5,
ADC_SAMPLE_TIME_55_5,
ADC_SAMPLE_TIME_71_5,
ADC_SAMPLE_TIME_239_5,
}adc_sample_time;
#define ADC_CHANNEL_0 ( 0x00000000U)
#define ADC_CHANNEL_1 ( 0x00000001U)
#define ADC_CHANNEL_2 ( 0x00000002U)
#define ADC_CHANNEL_3 ( 0x00000003U)
#define ADC_CHANNEL_4 ( 0x00000004U)
#define ADC_CHANNEL_5 ( 0x00000005U)
#define ADC_CHANNEL_6 ( 0x00000006U)
#define ADC_CHANNEL_7 ( 0x00000007U)
#define ADC_CHANNEL_8 ( 0x00000008U)
#define ADC_CHANNEL_9 ( 0x00000009U)
#define ADC_CHANNEL_10 ( 0x0000000AU)
#define ADC_CHANNEL_11 ( 0x0000000BU)
#define ADC_CHANNEL_12 ( 0x0000000CU)
#define ADC_CHANNEL_13 ( 0x0000000DU)
#define ADC_CHANNEL_14 ( 0x0000000EU)
#define ADC_CHANNEL_15 ( 0x0000000FU)
#define ADC_CHANNEL_16 ( 0x00000010U)
#define ADC_CHANNEL_17 ( 0x00000011U)
#if defined(use_adc) || defined(use_adc_dma)
void ADC_init (void);
void ADC_addChannelToScanList (u8 channel);
void ADC_removeChannelFromScanList (u8 channel);
// configure DMA and start conversion
void ADC_startConversionDMA (u8 channels, u16 * ADC_array);
// configure DMA only. Conversion will be triggered lately by software or by hardware
// through an event
void ADC_configureDMA (u8 channels, u16 * ADC_array);
u8 ADC_disable (void);
u8 ADC_enable (void);
#endif
/*========================================================================================*
* DMA MACROS
*========================================================================================*/
typedef enum {
DMA_MSIZE_8_bit = 0,
DMA_MSIZE_16_bit,
DMA_MSIZE_32_bit
}dma_msize;
typedef enum {
DMA_PSIZE_8_bit = 0,
DMA_PSIZE_16_bit,
DMA_PSIZE_32_bit
}dma_psize;
typedef enum {
DMA_PRIO_LOW = 0,
DMA_PRIO_MEDIUM,
DMA_PRIO_HIGH,
DMA_PRIO_VERY_HIGH,
}dma_prio;
#define DMA_SET_NDATA(dma_channel, n) dma_channel->NDT = n
/*========================================================================================*
* CRC
*========================================================================================*/
void crc_reset (void);
u32 crc_compute (u32* start_address, u32* end_address);
u32 crc_get (void);
#endif /* MCU_h */
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